Altera introduced their Embedded Initiative, which will give designers a single FPGA design flow based on the Quartus II development software. The design flow features the Qsys system-level integration tool, a common FPGA intellectual property (IP) library, and the ARM Cortex-A9 MPCore and MIPS Technologies MIPS32 embedded processors. The Qsys system-level integration tool leverages FPGA-optimized network-on-a-chip technology to support a wide variety of industry-standard IP protocols.
The Embedded Initiative enables embedded designers to quickly and easily target Altera’s Nios II, ARM- and MIPS-based embedded processors and the configurable Intel Atom-based processor. The FPGA flow reduces overall system cost, achieves faster time to market and increases the flexibility of system designs. The Embedded Initiative is ideal for automotive, industrial, military and wireless applications.
As part of the Embedded Initiative, Altera will expand its current embedded partner programs by embracing the broad ecosystems from ARM, Intel and MIPS Technologies, as well as the FPGA world. In addition, Altera will collaborate with these partners to enhance the design flow and allow access to the growing number of FPGA-enabled embedded processing choices.
Earlier this year, Altera also signed an agreement with ARM Ltd. to license a range of technologies, including the Cortex-A9 microprocessor. Altera will deliver products that integrate hardened Cortex-A9 processor-based subsystems with 28-nm FPGA technology.
Altera has also broadened its portfolio of soft processor cores and will introduce the MP32 soft processor core based on MIPS Technologies’ MIPS32 processor architecture in early 2011. The MP32 is a result of close collaboration between Altera, MIPS Technologies and lead customers over the past year. It will complement Altera’s Nios II embedded processor and the portfolio of partner soft CPUs available for Altera devices, and significantly extend the number of operating systems and the amount of application code available for use on FPGAs.
Later this quarter, Altera will deliver the Qsys system integration tool, as part of the Quartus II development software. Qsys is the first to feature FPGA-optimized network-on-a-chip technology. Qsys will be able to offer memory-mapped and datapath interconnects that achieve nearly double the performance of Altera’s SOPC Builder tool, while being able to support industry-standard IP interfaces, such as AMBA. Qsys will leverage the easy-to-use interface of SOPC Builder and provide backwards compatibility for easy migration of existing embedded systems. In addition, this advanced interconnect technology will support hierarchical design, incremental compile and partial reconfiguration methodologies.
More information: Altera