Altera and ARM have developed a DS-5 embedded software development toolkit with FPGA-adaptive debug capabilities for Altera SoC devices. The ARM Development Studio 5 (DS-5) Altera Edition toolkit is designed to remove the debugging barrier between the integrated dual-core CPU subsystem and FPGA fabric in Altera SoC devices. The toolkit will be included in the Altera SoC Embedded Design Suite (Altera SoC EDS) Subscription Edition for $995. It will start shipping in early 2013.
The new toolkit provides embedded software developers an unprecedented level of full-chip visibility and control through the standard DS-5 user interface. It combines a multi-core debugger for the ARM architecture with the ability to adapt to the logic contained in the FPGA.
The ARM Development Studio 5 (DS-5) Altera Edition toolkit dynamically adapts to configurations of the FPGA within the SoC to seamlessly extend embedded debugging capabilities across the CPU-FPGA boundary and unify all software debugging information from the CPU and FPGA domains with the standard DS-5 user interface. When combined with the multi-core debugging capability of the DS-5 Debugger, and the link to the Quartus II software SignalTap logic analyzer forcross-triggering capability, the toolkit delivers an unprecedented level of debugging visibility and control that leads to substantial productivity gains.
The ARM DS-5 toolkit suite offers the most advanced multi-core debugger in the market for the ARM architecture. It supports debugging on systems running in asymmetric multiprocessing (AMP) and symmetric multiprocessing (SMP) system configurations. It is broadly used for board bring-up, driver development, OS porting, bare-metal and Linux application development, through JTAG and Ethernet debugging interfaces, and offers Linux and RTOS awareness.
ARM DS-5 Altera Edition Toolkit Features
- Software debug view adapts to include the peripheral devices programmed by the developer into the FPGA fabric, providing a seamless view of both the hard and soft peripheral register memory map of the entire SoC
- The DS-5 Debugger simultaneously displays debug/trace data for the Cortex-A9 processor cores and CoreSight-compliant custom logic cores implemented in the FPGA fabric
- Altera USB-Blaster JTAG debug cable supports both the DS-5 debugger and other Altera JTAG-based tools for the Altera SoC device
- Allows non-intrusive capture and visualization of signal events in the FPGA fabric that can be time-correlated with software events and processor instruction trace
- Supports advanced, signal-level hardware cross-triggering between the CPU and FPGA logic domains, which enables cross-domain hardware/software co-debugging
- Includes the DS-5 Streamline performance analyzer, which correlates software thread and event information with hardware counters from both the SoC and FPGA, enabling the identification and correction of system-level bottlenecks