Altera Cyclone V and Arria V SoC FPGA Families

Altera launched their new ARM-based SoC FPGA family. The devices feature 28nm Cyclone V and Arria V FPGA fabric, dual-core ARM Cortex-A9 MPCore processor, error correcting code (ECC) protected memory controllers, peripherals and high-bandwidth interconnect on a single chip. Altera’s Cyclone V and Arria V SoC FPGA silicon will be available in the second half of next year. Prices of the new system-on-chip field programmable gate arrays start at less than $15.

Altera Cyclone V and Arria V SoC FPGA

Altera Cyclone V and Arria V SoC FPGA Features

  • Dual-core ARM Cortex-A9 MPCore processor
  • Up to 800 MHz maximum frequency
  • Symmetric multiprocessing (SMP) and asymmetric multiprocessing (AMP)
  • Processor and DMA access to FPGA peripherals
  • Configurable 32-, 64-, or 128-bit advanced microcontroller bus architecture (AMBAR) Advanced eXtensible Interface (AXI)
  • FPGA masters access processor subsystem peripherals
  • Configurable 32-, 64-, or 128-bit AMBA AXI interface
  • Coherent access to processor cache through ACP
  • FPGA-to-HPS SDRAM controller subsystem interface
  • FPGA access to DRAM for shared or unified memory
  • Up to 6 masters, 4 x64-bit read, 4 x64-bit write data
  • FPGA-to-HPS interrupts
  • DMA handshake (allows FPGA peripherals to perform block-level transfers with system DMA controller)
  • More than 100 Gbps HPS-to-FPGA and FPGA-to-HPS bandwidth
  • Multiport SDRAM controller
  • Flash memory controller
  • Two 10/100/1000 Ethernet media access controllers (EMACs) with DMA
  • Two USB 2.0 On-The-Go (OTG) controllers with DMA
  • Four I2C controllers
  • Two controller area networks (CAN), SPI Master, SPI Slave, UART
  • Up to 71 general-purpose I/0s (GPIOs) and 15 input-only
  • Four general purpose timers
  • Two watchdog timers
  • 8-channel DMA controller
  • FPGA manager
  • Clock and reset managers
  • 64 KB on-chip RAM
  • Boot ROM

More info: Altera