LatticeXP2 HiSPi to Parallel Sensor Bridge Reference Design

Lattice Semiconductor introduced a HiSPi bridge reference design that supports Aptina’s High-Speed Serial Pixel Interface. The reference design is based on LatticeXP2 FPGA devices, which can support four HiSPi data lanes up to 700Mpbs. The HiSPi bridge solution enables an Image Signal Processor (ISP) with a CMOS parallel bus to interface with an Aptina HiSPi CMOS sensor. The free reference design supports all modes of the Aptina HiSPi specification. The LatticeXP2 HiSPi bridge reference design is ideal for security cameras, automotive applications, and high end consumer cameras.

Aptina HiSPi to Parallel Sensor Bridge reference design - Lattice Semiconductor LatticeXP2 FPGA

Aptina HiSPi Bridge Reference Design Highlights

  • Supports HiSPi formats Packetized-SP, Streaming-SP, Streaming-S or ActiveStart-SP8
  • Supports one to four lanes, running at up to 700 Mbps each
  • Supports HDR or linear mode
  • Common HiSPi interface designs can be downloaded
  • HiSPi configuration tool for generating a specific HiSPi bridge
  • Designed to emulate parallel sensor output
  • Output bus widths of 10, 12, 14 or 16 bits
  • Bridge device offered in 8×8 mm 132csBGA
  • TQFP packages also available
  • Does not require external PROM
  • Tested with TI TMS320DM8127 and TMS320DM36X ISPs, and Aptina MT9M034, MT9M024 and MT9J003 sensors
  • Parallel interface can be configured for 1.8V, 2.5V or 3.3V LVCMOS levels
  • The Lattice XP2-5 is available in commercial, industrial or automotive qualified temperature ranges
  • Ideal for security cameras, automotive applications, high end consumer cameras and other camera applications

More info: Lattice Semiconductor | Aptina