PLDA QuickUDP 10Gb UDP Hardware Stack IP Core for Altera and Xilinx FPGAs

PLDA QuickUDP 10Gb UDP Hardware stack IP core for FPGA devices

PLDA introduced their QuickUDP, which is a 10Gb UDP Hardware stack IP core for FPGA devices. The QuickUDP IP solution is a 100% RTL-designed IP, compliant with the IEEE802.3 specification and supports the ARP, IPv4, ICMP, IGMP, and UDP protocols. The PLDA QuickUDP 10G UDP Hardware Stack IP is available now from PLDA. The PLDA QuickUDP can be integrated into Altera-based and Xilinx-based FPGA designs.

PLDA QuickUDP IP for FPGA features full RTL Layers 2, 3, 4 implementation with integrated 10G Ethernet MAC, and an integrated Layer 1 XGMII PHY interface. The 10G UDP Hardware Stack IP supports up to 256 UDP connections with an easy-to-use Avalon-ST or AMBA AXI4 user interface that enables instant integration into either Altera-based or Xilinx-based FPGA designs.

PLDA QuickUDP Features

  • Supports Xilinx Virtex-7 and Kintex-7, and Altera Stratix IV GX/GT and Stratix V GX/GS/GT FPGAs
  • Management of layers 1, 2, 3 and 4 (OSI Model)
  • Compliant Layer 1: IEEE802.3
  • Compliant Layer 2: IEEE802.3, ARP (Address Resolution Protocol)
  • Compliant Layer 3: IPv4, IGMP v2, and ICMP (Internet Control Message Protocol)
  • Compliant Layer 4: UDP
  • UDP management with up to 256 connections in each direction
  • MTU (Maximum Transmission Unit) up to 9000 bytes payload for supporting Standard and Jumbo Ethernet frames
  • Hardened ICMP Client and ARP Server/Client
  • VLAN configurable at runtime
  • Supports Unicast and Multicast transmit/receive
  • Supports IGMP v2 Membership Report/Leave
  • Avalon Streams user interface for data
  • 64-bit wide interface running at 156.25-MHz for UDP client port
  • 64-bit wide interface running at 156.25-MHz for MAC client port (UDP bypass)
  • PHY interface with XGMII interface to integrated XAUI PHY or 10G PMA-PCS
  • PHY/SFP management
  • MDIO (Management Data I/O) master controller for External 10G transceiver management
  • I2C (Inter Integrated Circuit) master controller for QSFP/SFP module management
  • 32-bit AXI4Lite slave control interface for MAC, UDP configuration and MDIO/I2C access

More info: QuickUDP IP for Altera FPGA | QuickUDP IP for Xilinx FPGA