Altera Quartus II Version 8.1

Altera Corporation (NASDAQ:ALTR) announced version 8.1 of its Quartus® II software. The new release of Quartus II software continues to deliver high-density FPGA compile times three times faster than other FPGA-vendor supplied development software, based on internal benchmarks. The enhanced productivity features within Quartus II software enable design teams to close timing and power faster, lower R&D costs and shorten time to market. Both the subscription edition and the free web edition of Quartus II software version 8.1 are available for download now. The Subscription Edition is also available in DVD format by request.

Faster Design Development
While next-generation FPGAs deliver a greater level of functionality, design teams continue to be constrained by limited development times. Quartus II software version 8.1 helps speed development times by automating traditionally time-consuming features. The design partition planner, introduced in the previous version of Quartus II software, now provides automated partitioning in version 8.1, allowing more designers to leverage the productivity benefits of incremental compilation. Quartus II software now also eliminates the need to modify gated clocks manually by automatically converting gated clocks to functionally equivalent logic supported by the FPGA architecture. Automating these features allows design teams to focus more effort on value-added portions of the design.

Expanded Device Support
Altera cemented its leadership position in the high-performance, high-density FPGA market with the launch of its 40-nm Stratix® IV FPGAs in May 2008. To date, nearly 600 customers are part of Altera’s Stratix IV early adopter program, and many have started designing Stratix IV FPGAs into applications across all of Altera’s market segments using Quartus II software. Version 8.1 provides an even greater level of support to these customers by adding Stratix IV pin-outs and support for a new Stratix IV FPGA speed grade offered in a low-cost package. The software provides added transceiver timing-model support, as well as support for 8.5-Gbps transceivers, 1.6-Gbps LVDS and 400-MHz DDR memory. For designers targeting a HardCopy ASIC implementation, Quartus II software provides initial support for HardCopy IV ASICs.

Quartus II 8.1 Features

  • More control and flexibility
    Enhanced task window allows user-defined development flows
  • SignalTap® II Embedded Logic Analyzer
    Finer data-sampling control speeds debugging and improves on-chip memory efficiency
  • Enhanced SOPC Builder Tool
    • New HDL templates enhance the speed and ease for which SOPC Builder can be used for intellectual property (IP) reuse
    • A new Avalon(R) memory-mapped half-rate bridge is available for low-latency access for DDR SDRAMs
  • New operating system support
    Red Hat Enterprise Linux 5 and CentOS 4/5 (32-bit/64-bit)
  • Enhanced third-party simulation interface
    Automatic compilation of library files for faster simulation setup
  • New Pin-Out Advisor
    Guides pin-out creation and interface with third-party board tools
  • Real Intent Verification Support
    Real Intent’s Meridian FPGA Clock Domain Crossing (CDC) software offers easy-to-use automatic clock intent verification to catch design errors and create confidence in reliable CDC operations
  • New and enhanced IP cores and megafunctions
    Digital signal processing (DSP), memory and protocols accelerate development
  • Physical synthesis engine enhancements
    Improve performance of timing-critical blocks in 20 percent less time on average than the previous version for faster timing closure
  • Synopsys Design Constraints (SDC)
    SDC templates guide and accelerate timing constraint creation

More information: Altera Quartus II Software Version 8.1