Altera (NASDAQ: ALTR) shipped their EP3SL150, which is the first member of its 65-nm Stratix(R) III FPGA family. The EP3SL150 features 150K logic elements and delivers the lowest power consumption of any high-density, high-performance programmable logic device. The EP3SL150 is ideal for a broad range of applications such as high performance computing, next-generation basestations, network infrastructure, and advanced imaging equipment.
Stratix III FPGAs offer both 45% lower power consumption and a 25% performance advantage over competing solutions. The combination of Stratix III FPGAs and Altera(R) Quartus(R) II design software improves productivity as well as performance. For example, in the area of memory interfaces, the Stratix III FPGAs provide designers with the industry’s only fully compliant interface support for the newly ratified JEDEC DDR3 SDRAM standard, including read and write leveling to DIMMs as well as devices.
To dramatically lower power while simultaneously delivering high performance, Stratix III FPGAs feature Altera’s innovative Programmable Power Technology. This power management technology enables every programmable logic array block (LAB), digital signal processing (DSP) block and memory block to operate independently at high-speed or low-power mode. The PowerPlay feature in Quartus II software automatically controls the mode of each block based on performance requirements. Another unique power saving feature is the Selectable Core Voltage, which allows designers to choose 1.1V core voltage for high-performance applications or 0.9V core voltage for the lowest power consumption.