Altera EFEC7 and EFEC20 100G IP Cores

Altera introduced the EFEC7 and EFEC20 enhanced forward error correction (EFEC) IP cores. The multi-dimensional IP cores are optimized for high performance Stratix IV and Stratix V series FPGA devices. The EFEC7 and EFEC20 were developed by Altera’s Newfoundland Technology Centre (formerly Avalon Microelectronics). They are ideal for 100G applications such as metro and long-haul optical transport networks (OTN). According to Altera, they are the first company to offer an integrated, single source 100G solution.

Altera EFEC7 enhanced forward error correction (EFEC) IP core for 100G

EFEC7 and EFEC20 100G IP Cores Features

  • Supports G.709 OTU-4
  • Streaming Turbo Product Code BCH code (SPC-BCH)
  • > 9.2dB net coding gain at 10-15 output BER with 6.7% OTN overhead (EFEC7)
  • > 10dB net coding gain at 10-15 output BER with 20% OTN overhead (EFEC20)
  • Generic CPU interface for control and monitoring
  • 7% overhead ratio (EFEC7)
  • 20% overhead ratio (EFEC20)
  • Available statistics:
    • Corrected bits
    • Corrected ones
    • Corrected zeros
    • Final iteration uncorrectable codes
  • Smallest FPGA-based 100G EFEC implementation available
  • Enables increased transmission distance or lower transmission power
  • Supported by Altera Stratix IV and Stratix V FPGAs

More info: Altera