Altera at DesignCon 2008

Altera Corporation (NASDAQ:ALTR) will showcase how its FPGA architectural innovations and technologies enable high-speed I/O performance, best-in-class signal integrity, and low power consumption at DesignCon 2008. Altera will also keynote a presentation, conduct product demonstrations in its booth, and present 10 technical papers. More information about Altera at DesignCon 2008 is listed below:

Keynote Presentation

Programmable Solutions: A Continued Evolution
Dr. Misha Burich, senior vice president of research and development
February 5, 2008, 12:00 PM to 12:30 PM

Now, more than ever before, there is pressure in the electronics industry to shorten time-to-market, to lower development costs, and offer product variations and options. To satisfy these requirements, the semiconductor industry continues to innovate in providing programmable solutions that can be rapidly adapted by their customers and deployed to their end users. Dr. Misha Burich will describe promising current and future technologies that satisfy these requirements, including the spectrum from fine-grained to coarse-grained multi-cores and rapidly customizable ASSP solutions.

Technical Papers

Tuesday, February 5

  • 8:30 AM – 9:10 AM: “Analysis of Crosstalk Effects on Jitter in Transceivers”
  • 10:15 AM – 10:55 AM: “Study of Fundamental Limit and Packaging Technology Solutions for 40-Gbps Transceiver Package Design”
  • 11:05 AM – 11:45 AM: “A Reset Control Apparatus for PLL Power-Up Sequence and Auto-Synchronization”

Wednesday, February 6

  • 8:45 AM – 9:25 AM: “Using Programmable Logic for Receiver Offset and Yield Enhancement”
  • 8:45 AM – 9:25 AM: “A Fast Algorithm to Instantly Predict FPGA SSN for Various I/O Pin Assignments”
  • 8:45 AM – 9:25 AM: “A Jitter Estimation Method for Cascaded, Programmable Phase-Locked Loops”
  • 9:40 AM – 10:20 AM: “Challenges in Implementing DDR3 Memory Interface on PCB Systems: A Methodology for Interfacing DDR3 SDRAM DIMM to an FPGA”
  • 2:00 PM – 2:40 PM: “Process and Temperature Variations on Electrical Parameters of Wire-Bond BGA Packages: an Impact Analysis Using Simulation-Based DOE Methodology”
  • 2:50 PM – 3:30 PM: “FPGA I/O Timing Variations Due to Simultaneous Switching Outputs”
  • 2:50 PM – 3:30 PM: “Modeling FPGA Current Waveform, Spectrum & PDN Noise Estimation”


  • Stratix III FPGA – Programmable Power Technology
    • Delivers up to 50 percent lower power with 35 percent higher performance and 2X higher density compared to previous-generation devices
  • Stratix III FPGA – 1067-Mbps DDR3 Memory Interface
    • Provides JEDEC-compliant DDR3 1067-Mbps DIMM capability through read/write leveling with added power savings through dynamic on-chip termination (OCT) and the low supply voltage of DDR3 memory
  • Stratix II GX FPGA – Dynamic Reconfiguration
    • Dynamically changes transceiver data rates, protocols and PMA settings without interrupting other channels
    • Dynamically optimizes signal integrity for backplane applications up to 6.375 Gbps
  • Stratix II GX FPGA – Plug & Play Signal Integrity
    • Automatically reconfigures backplane equalization settings
    • Automatically maintains optimal signal integrity at high data rates
  • 10-Gbit Test Chip
    • Demonstrates the robust performance margins and optimal signal integrity in Altera’s transceiver technologies

DesignCon 2008
February 4 to February 7, 2008
Santa Clara Convention Center
Booth 429
Santa Clara, Calif.

More info: Altera at DesignCon 2008