Altera has an On-Demand webcast about implementing high-speed DDR3 interfaces. The webinar will discuss the challenges of implementing DDR3 and available solutions. The event is targeted at system architects, hardware and system design engineers, FPGA developers, and signal integrity engineers.
With today’s requirements for high-speed memory interfaces surpassing 1 Gbps, FPGA silicon and IP must be designed to provide robust signal integrity and address the challenges of implementing DDR3 interfaces. Simulation still plays an important role in validating signal levels and timing margins. Altera’s webcast will discuss:
- The JEDEC requirements for DDR3
- How to address read/write leveling in your system
- How to reduce power consumption on your board and track PVT
More info: Implementing High-Speed DDR3 Interfaces