High-Definition Wide Dynamic Range Video Surveillance Chipset

Altera, Apical, and AltaSens teamed together on a chipset for HD WDR video surveillance. The new chipset features an Altera Cyclone IV E FPGA and a security chip that supports Apical’s HD WDR full image signal processing (ISP) pipeline IP and AltaSens’ 1080p60 A3372E3-4T image sensor. Engineers can download the evaluation IP, Apical’s Image Signal Processing Evaluation Design, before purchasing the HD WDR video surveillance chipset.

Apical's HD WDR full image signal processing (ISP) pipeline IP

HD WDR Video Surveillance Chipset Highlights

  • Altera Cyclone IV E FPGA
  • Pre-programmed security device with support for Apical’s HD WDR full image signal processing (ISP) pipeline IP
  • AltaSens’ 1080p60 A3372E3-4T image sensor technology
  • Simplifies the development of a video surveillance camera system
  • Provides a single vendor source for the IP and the FPGA
  • Apical’s Image Signal Processing Evaluation Design (evaluation IP) can be downloaded before purchasing chipset
  • After evaluation, the Image Signal Processing IP core license can be downloaded and incorporated into a FPGA design via the Quartus II software
  • Ready-made and programmable chipset
  • Reduces development time and increases design flexibility
  • Apical’s HD HDR full image signal pipeline IP is optimized for the Altera Cyclone IV E FPGA
  • First time AltaSens sensors have been supported in a chipset

More info: Altera | Apical | AltaSens