Aldec Active-HDL v9.1 FPGA Design and Simulation Tool

Aldec launched verion 9.1 of the Active-HDL FPGA Design and Simulation solution. Active-HDL v9.1 features auto-complete technology built into the HDL Editor, language templates, phrase highlighting, enhanced level of automation, and new HDL code browser tool that can detect errors in the source code even before compilation. The HDL-based tool supports design creation and simulation of the newest FPGA devices from Altera, Atmel, Lattice, Microsemi (Actel), Tabula, Quicklogic and Xilinx.

Active-HDL 9.1 Highlights

  • Push button integration with Aldec’s ALINT and Riviera-PRO to provide a gateway to 64-bit simulation and SystemVerilog verification
  • HDL Code Browser Tool for on-the-fly error detection prior to compilation
  • Unified Coverage Database for generating and managing different types of coverage more efficiently
  • Extended documentation support to assist in DO-254 compliance requirements
  • Improved signals handling on the waveform — option to keep the signals on the waveform when simulation is re-initialized
  • Takes advantage of all the enhancements made to VHDL-2008, Verilog and SystemVerilog (design construct)
  • Improved debugging of Block Diagram components
  • Enhanced support of VHDL-2008 and PSL/SVA assertions
  • Time-saving new features within the HDL Editor
  • Improvements to the Block Diagram Editor and Waveform Viewer
  • Robust auto-complete technology built into the HDL Editor
  • Language templates
  • Phrase highlighting
  • Supports the latest FPGA devices from Altera, Atmel, Lattice, Microsemi (Actel), Tabula, Quicklogic and Xilinx

More info: Aldec Active-HDL