The Synfora PICO Extreme and PICO Extreme FPGA algorithmic synthesis design tools now feature higher performance and smaller area. The new enhancements enable designers to create and analyze hardware designs more effectively, and include QoR (Quality of Results) improvements in terms of area, throughput, timing and timing correlation, as well as user feedback improvements. PICO Extreme is an advanced optimizing compiler that transforms a sequential, untimed C algorithm into highly efficient RTL (Register Transfer Language), reducing design and verification time, allowing designers to find the lowest cost implementation and enabling very rapid reaction to changes in the design specification.
The new version of PICO Extreme features improved scheduling algorithms taht enable the compiler to optimize registers in a design. In a suite of 50 actual customer designs, this yielded area improvements in the range of from 5% to 20 %, with a corresponding reduction in silicon cost. Sophisticated analysis of variable loop bounds, combined with an innovative new approach to handling early exits from loops, provides performance improvements in the 10% to 30% range on complex designs.
Achieving high productivity on complex designs requires that synthesis tools provide the user with sophisticated analysis, feedback, and debugging capabilities to understand the performance and area bottlenecks in the design. The enhancements to PICO Extreme 08.03, including those to the reporting and feedback capabilities, improve the ability to analyze throughput bottlenecks, provide greater visualization and reporting of the hardware cost, and allow automatic detection and feedback on potential deadlock scenarios.