Using HDL Simulation for Xilinx Virtex-5 FPGAs

Nu Horizons Electronics is offering a seminar titled “Using HDL Simulation for Xilinx Virtex-5 FPGAs.” The event will take place from 9:00am to 1:30pm on July 22nd, 2008 in San Jose, CA. Lunch and refreshments will be provided. The seminar features hands-on labs and is intended for Design Engineers, Verification Engineers, and EDA Tool Managers.

Blurb:

Designers of modern FPGAs face large variety of challenges while working on their projects: they require speed tget results quickly, but high-end debugging features and good visibility of design elements is alsin demand. The ability toptimize your tool performance and set debugging options properly is critical, letting you get better results faster and increasing your job security.

The workshop (lecture with labs using Xilinx design as a vehicle) will show the attendees how tfine-tune simulations for maximal speed / most efficient debugging and present the latest, advanced verification techniques in action. The topics covered in presentation include: managing projects in Aldec Riviera-PRO, optimizing compilation and simulation, debugging techniques (smart waveform comparison, various flavors of coverage, etc.) and design analysis (design profiling and linting).

Topics

  • Overview
  • Getting Started with Riviera-PRO
    Lab1
  • High Performance Xilinx Simulation
    Lab2
  • Debugging the Design
    Lab3
  • Waveform Compare
    Lab4
  • Automatic Testbench Generation
    Lab5
  • Coverage Tools
    Lab6
  • Profiling and Linting
    Lab7

More info: Using HDL Simulation for Xilinx Virtex-5 FPGAs Seminar