Aldec Active-HDL Designer Edition for FPGA

The Aldec Active-HDL Designer Edition is a low-cost mixed language RTL simulator. The tool includes IEEE mixed-language simulation support for VHDL, Verilog and SystemVerilog (Design), 2X-plus performance gains over FPGA vendor supplied RTL simulators, encrypted IP support, and no performance limitations on FPGA design size. Active-HDL Designer Edition is available now and supports Windows 32/XP/Vista operating systems. The mixed language RTL simulator is offered as a one year time based license and available as either a node locked ($1,995) or floating ($2,495) license.

Active-HDL Designer Edition Features

  • Mixed-language simulator
    VHDL IEEE 1076 (1987, 1993, 2002 and 2008), Verilog HDL IEEE 1364 (1995, 2001 and 2005), SystemVerilog IEEE 1800 (Design)
  • Performance
    2X+ faster performance then FPGA vendor simulators on average
  • Debugging
    Waveform viewer, memory viewer and code execution tracing
  • Encrypted IP
    IEEE VHDL and Verilog IP support
  • Unlimited Device Size support
  • HDL design tools
    Mixed-language design entry, state machine, block diagram, and HDL editor
  • Design Flow Manager
    Integrates third-party tools (synthesis and place/route 85 sub applications)
  • Windows 32/XP/Vista
  • One year time based license

The Aldec Active-HDL Designer Edition closes a gap in the mixed RTL FPGA simulation market. Currently, FPGA designers can purchase a high performance mixed language RTL simulator from Aldec or other commercial EDA vendors starting at $6,000 or alternatively purchase a restricted, single language, FPGA vendor supplied simulator for $1,000 or less. A price, feature, and performance gap exists between the commercial EDA simulators and the FPGA vendor simulators. Active-HDL Designer Edition fills this market gap and provides FPGA designers with a mixed language simulator for less than $2,000.

More information: Aldec