Rapid ASIC Emulation in FPGA with HES Webinar

Aldec will host a webinar titled, Rapid ASIC emulation in FPGA with HES. The webcast will take place Thursday, September 18 at 3:00 PM Central European Summer Time (CEST). The presenter will be Jaroslaw Kaczynski, Technical Marketing Engineer.

Agenda

  • Cross-FPGA design partitioning with signal multiplexing
  • External stimulus synchronization
  • Driving the emulation
  • Integration with prototyping boards

Abstract

We will explain how an ASIC design can be setup for emulation at 1 to 5 MHz using Design Verification Manager (DVM) – a part of ALDEC’s HES product line. Aldec developed several revolutionary algorithms of FPGA partitioning and cross-chips synchronization that guarantees your ASIC up and running in FPGAs in just a few hours.

More info: Rapid ASIC Emulation in FPGA with HES