Aldec EDA Verification Suite Enhancements

Aldec, Inc. announced improvements to their EDA verification suite. The enhancements include all RTL software simulators, HDL verification, hardware-assisted verification, and specialty solutions development platforms. In addition, Aldec verification suite incorporates advanced and innovative design methodologies, such as ESL, module-based design and transaction level modeling, OVM and VMM.

  • Hardware-Assisted Verification
    Hardware assisted verification is also available in Aldec’s enhanced verification suite. Transaction Level Modeling (TLM) with SCE-MI 2.0 for high-performance emulation at 10MHz, using off-the-shelf The Dini Group and Synopsys/Synplicity HAPS boards for large and complex ASIC & SOC designs from 1 million to 32 million ASIC gates. Aldec emulation provides automatic conversion from ASIC to FPGA, simple design setup and multi-chip partitioning, automatic design compilation. Transaction Level Modeling (TLM), which is based on the SCE-MI 2.0 standard from Accellera, allows for more productive test development with higher levels of abstraction, emulating C++/SystemC transaction level testbenches in high-performance in-hardware speeds. Aldec automates the insertion of SCE-MI transactor into the user’s design and provide SCE-MI API functions to interface to the transactor from the software side. Aldec hardware can automatically download into an FPGA board, an Electronic System Level (ESL) design that includes processors and memories. These processors and memories can be exercised at system level clock speeds of up to 10MHz, engineers can run real RTL in real hardware, at close to speed, and perform all the test cases needed.

  • System Level Verification
    Aldec verification products provide System-level verification solutions utilizing SystemC with its transaction-level models (TLMs) and SystemVerilog verification methodologies.

  • SystemC
    Modeling the behavior of the entire system using a high-level language such as C, C++, or MATLAB is easy; Aldec’s verification suite includes seamless integration of SystemC/C++ debugging with mixed HDL debugging, crucial for Electronic System Level (ESL) designers. This new level of integration enables identical procedures for tracing source code, setting breakpoints, viewing objects, whether in SystemC or HDL.

  • SystemVerilog
    Aldec verification suite supports IEEE 1800TM SystemVerilog, a unified hardware description and verification language. Aldec verification suite supports all three groups of constructs: design, assertions, and verification; most recent improvements were added in strings, classes and DPI areas, with the current and future construct support, interoperable SystemVerilog verification methodologies, including both Open Verification Methodology (OVM) and Verification Methodology Manual (VMM).

  • OVM and VMM Support
    Aldec is developing the support of OVM 1.1 and its robust class library and source code for integration throughout its entire verification suite. OVM is based on IEEE 1800 SystemVerilog standard and is for design and verification engineers developing advanced verification environments that offer higher levels of integration and portability of verification IP. In addition, Aldec is also developing support for the newly donated Accellera Verification Methodology Manual (VMM), which shows how to use SystemVerilog to create comprehensive verification environments utilizing coverage-driven, constrained-random and assertion-based techniques, and library building blocks for creating interoperable verification components.

  • Assertions and Functional Coverage
    Aldec verification products support properties, assertions and covers expressed in SystemVerilog (SVA) and Property Specification Language (PSL). During regular simulation runs users can observe standard messages generated by assert or cover directives. Breakpoints can be set on assertions to pause simulation at critical points; current status of assertions and covers can be observed graphically in the Waveform Viewer and extensive statistical data is available in enhanced Assertion and Cover Viewers. For improved flexibility of design management, assertions can be specified in separate, dedicated files or placed directly in the design code.

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