Lattice PAC-Designer 4.99a

Lattice Semiconductor (NASDAQ: LSCC) released version 4.99a of its PAC-Designer® software design tool suite. The tool suite now supports Lattice’s AECQ100-qualified automotive Power Manager II (LA-ispPAC®-POWR1014/A) devices. The PAC-Designer tool suite also provides easy to use, point-and-click, intuitive design and verification support for all Power Manager and ispClock[TM] mixed signal devices. The PAC-Designer software is available now and can be downloaded free of charge.

Common power management functions found on circuit boards include hot-swap control, voltage supervision, supply sequencing and reset generation. To ensure board reliability, all board-mounted power supplies should be sequenced and monitored via a power management algorithm. Typically, the power management algorithm is either changed or fine tuned during the board debug process to meet unforeseen device power-up behavior. Traditional solutions are hard-wired and cannot be changed without an expensive board re-spin. Lattice’s Windows-based PAC-Designer software enables implementation of a new power management algorithm in Lattice’s Power Manager II devices within minutes.

Similarly, clock network designs require timing adjustments during the board debug phase. The Lattice ispClock devices support an in-system programmable skew mechanism. Using the PAC-Designer software, designers can precisely alter the clock skew of each of the clock nets. Traditionally, clock skew has been implemented by “snaking” clock traces on the board, and any change to the skew was implemented through a time consuming, expensive board re-spin. Using the PAC-Designer software, the clock network skew is altered simply by reprogramming the ispClock device.

More info: Lattice Semiconductor