Aldec, Inc. released Active-HDL 8.1. The new release features a FPGA simulator that supports assertions and functional coverage in SVA, PSL and OVA at an affordable price. Other improvements in this release include Verilog® simulation performance speed-up and support for additional VHDL 2008 language constructs. Active-HDL is a mixed-language HDL simulator that offers project management, graphical design creation and support for all leading FPGA vendors from a single integrated design environment. Active-HDL is available in three Product Configurations – Designer Edition (DE), Plus Edition (PE) and Expert Edition (EE). The software is available in floating or node-locked configurations for the Windows operating system.
Active-HDL 8.1 Overview
Rapidly growing complexity of FPGA designs makes the introduction of property-based verification an important step to the support of assertions and functional coverage in Active-HDL 8.1. Design properties can be expressed in OVA, PSL or SystemVerilog languages and used in assertions or cover statements, placed directly in the HDL code of the design or in separate verification blocks.
Assertions and Functional Coverage
Assertions monitor behavior of the design and raise an alert when something undesired happens. Functional coverage ensures that all critical behaviors of the design were properly verified. Together they work as self-running safeguards, allowing designers to concentrate on creating a hardware description that simulates and synthesizes as expected. In addition to standard assert/cover messages printed to the console during simulation, Active-HDL enables numerous additional debugging features. Live status of assertions and covers can be viewed in the Hierarchy Browser and a dedicated Assertion Viewer, while global statistics of their execution are available in the Coverage Viewer. Breakpoints can be set on assertion activation, passing or failure events. The HDL Editor supports syntax highlighting for assertions and covers, and the updated Language Assistant makes adding them to the code much easier.
Verilog Simulation Speed-up
Verilog simulation speed at the gate level has been increased up to 2.3X over the previous releases by using the advanced optimization settings available within the simulator. All mixed-language designs will benefit from Verilog performance enhancements.
Other New Features
Active-HDL 8.1 includes enhanced support for VHDL 2008 (IEEE Standard P1076-2008) including new constructs and libraries. A new DPI-wizard to help create quick interfaces between SystemVerilog and C applications is now included in Active-HDL 8.1. The DPI-wizard allows simple entry of C/C++ tasks and functions and generates C wrappers, and sample SystemVerilog files. The wizard also creates a configuration file for compiling generated C files into a dynamic-link library. Active-HDL 8.1 supports new and updated libraries including: Assertions, OVL 2.2 and VTL.
More information: Aldec