Actel Corporation (Nasdaq: ACTL) enhanced its Libero(TM) Integrated Design Environment (IDE) to further ease the system-level design process when using its field-programmable gate arrays (FPGAs). With SmartDesign, a new design entry capability that enables users to design at a higher level of abstraction, Actel’s Libero IDE v8.0 significantly reduces FPGA design and development time, thus speeding customers’ time to market. The enhanced tool suite supports all the company’s FPGAs, including the flash-based, low-power ProASIC3 and 5 Micro Watt Actel IGLOO(TM) FPGAs, as well as the company’s single-chip Actel Fusion(TM) Programmable System Chip (PSC), a mixed-signal power management FPGA.
A key functionality within Libero IDE v8.0, SmartDesign lets users visually create and then automatically abstract block-based system designs into synthesis-ready VHDL or Verilog components. The graphical block-based design entry supports prefabricated blocks from Actel’s extensive DirectCore and SmartGen IP libraries. It also supports custom blocks created in HDL or Synplify(R) DSP and processor subsystems created with Actel’s CoreConsole tool.
Actel’s award-winning mixed-signal FPGA family, Fusion, receives additional support in Libero IDE v8.0 with the FlashPro 6.0 software update. Used with FlashPro programmers, this new version of the software further eases the programming of Actel’s IGLOO/e, ProASIC3 and Actel Fusion devices. A new feature in FlashPro, called FlashPoint, increases the flexibility in design finalization by allowing the user to modify and edit the FlashROM security settings independent of Libero or Designer. This saves the user from having to re-run the design through synthesis, place and route, and program file generation, significantly reducing overall design time.
The Actel Libero IDE 8.0 Platinum edition is available on Windows and Linux platforms for $2495. A limited feature Gold edition is available on Windows for free. All editions are one-year renewable licenses.