Achronix Speeds Time to Market with Verific Netlist-Only Parser

Achronix Semiconductor Corporation uses Verific’s Netlist-Only Parser in its Achronix CAD Environment (ACE). Achronix selected Verific’s Netlist-Only Parser to speed time-to-market and because it provided fast Verilog and EDIF parsing, plus a complete extendable netlist data structure and netlist manipulation functions. Achronix is the developer of Speedster FPGA, which is the world’s fastest field programmable gate array (FPGA). The Achronix Speedster family of FPGAs delivers speeds up to 1.5 gigahertz (GHz), a three-fold increase in performance over traditional FPGAs.

Verific Design Automation is known for its Verilog, SystemVerilog and VHDL hardware description level (HDL) parsers and elaborators. Its Netlist-Only Parser includes a Verilog netlist reader and a generic hierarchical netlist database to help reduce development time for products operating at the gate level rather than the register transfer level (RTL). As with all of Verific products, the Netlist-Only Parser is written in C++ and is shipped as source code.

More information: Achronix Semiconductor | Verific Design Automation