Achronix Semiconductor will demonstrate its Speedster FPGA’s 10.3 Gbps embedded serial-deserializer (SerDes) capability, a key element of its 1.5 GHz FPGAs. The demonstration will be at the FPGA Summit, Tuesday through Thursday Dec. 9-11, at the Wyndham Hotel in San Jose, Calif. Enabling applications such as 100 Gigabit Ethernet, the SerDes is an important element of the first member of the Achronix Speedster[TM] family, the SPD60, which delivers three times the performance of conventional FPGAs using patented picoPIPE technology. The SPD60 embeds 20 lanes of 10.3 Gbps SerDes and four independent embedded 1066 Mbps DDR2/DDR3 controllers.
Demonstrations will take place at Achronix’s booth #10, on Wednesday, Dec. 10, (from noon-2:00 p.m. and 5:00-7:00 p.m.) and Thursday, Dec. 11, (from noon-2:00 p.m.). Achronix will also be presenting on the topic, “GHz FPGAs for High Speed Applications,” Wednesday morning in the open session (8:30 a.m. – 9:45 a.m.) titled Communications and Networking Applications.