Altera announced the production availability of their 40-Gbps Ethernet and 100-Gbps Ethernet intellectual property cores. The cores can be used to create high-performance, low-cost, subsystem IP in Stratix IV and Stratix V FPGAs. Altera’s 40GbE and 100GbE IP cores are compatible with the recently announced Quartus II software v12.0. They are available for download on the Altera website.
The 40-Gbps Ethernet and 100-Gbps Ethernet IP cores are ideal for building systems requiring very high throughput-rate standard Ethernet connections — including chip-to-optical module, chip-to-chip, and backplane applications. The media access control (MAC) and physical coding sublayer plus physical media attachment (PCS+PMA) sublayer IP cores are IEEE 802.3ba-2010 standard compliant. This reduces design complexity for engineers integrating 40GbE and 100GbE connections on Altera’s 28-nm Stratix V FPGAs and 40-nm Stratix IV FPGA devices.
The 40GbE and 100GbE MAC and PHY IP cores provide an interface consisting of a single packet-based channel that is logically compatible with previous-generation Ethernet systems. The Altera cores are supported in Stratix V GT and GX FPGAs with transceivers operating at data rates up to 28.05 Gbps and 14.1 Gbps, respectively, and Stratix IV GT FPGAs with transceivers operating at data rates up to 11.3 Gbps. Stratix FPGAs combine high density, high performance and a rich feature set to help designers integrate more functions and maximize system bandwidth.