Altera is now shipping Stratix V FPGA devices in volume production. The Altera Stratix V devices are the only FPGAs to feature 14.1 Gbps transceiver bandwidth and are the only FPGAs capable of supporting the latest generation of the Fibre Channel protocol (16GFC). Altera started shipping engineering samples of 28nm FPGAs featuring integrated 14.1 Gbps transceivers over a year ago.
The transceivers in Stratix V GX and Stratix V GS FPGA devices offer high system bandwidth (up to 66 lanes operating up to 14.1 Gbps) at the lowest power consumption (under 200 mW per channel). Transceivers in Altera’s FPGAs feature advanced equalization circuit blocks, including low-power CTLE (continuous time linear equalization), DFE (decision feedback equalization), and a variety of other signal conditioning features for optimal signal integrity to support backplane, optical module, and chip-to-chip applications. The advanced signal conditioning circuitry enables direct drive of 10GBASE-KR backplanes using Stratix V FPGAs.
With the 28nm Stratix V FPGAs, developers of backplanes, switches, data centers, cloud computing applications, test and measurement systems and storage area networks can achieve higher data rate speeds as well as rapid storage and retrieval of information. For OTN (optical transport network) applications, Stratix V FPGAs enable carriers to scale quickly to support the giant growth of traffic on their networks.
The transceivers integrated in Altera’s Stratix V FPGAs include on-die instrumentation, low-jitter LC transmit PLLs (phase-locked loops), robust analog receive CDR (clock data recovery), and advanced transmit and receive equalization. In addition, Stratix V GT devices also feature the industry’s only 28-Gbps transceiver integrated in a single-chip, monolithic die. The transceivers featured in Stratix V FPGAs feature a full-featured physical coding sublayer (PCS) including, support for PCI Express Gen1/2/3, support for 40G and 100G datapath and extensive IP (intellectual property) library of industry-standard transceiver protocols.
More info: Altera Stratix V FPGAs