White Paper: Addressing 100-GbE Line-Card Design Challenges on 28-nm FPGAs

Altera published a white paper about how Altera FPGA devices are addressing 100-GbE line card design challenges. As various standard bodies finalize the 100G standards for transport, Ethernet, and optical interfaces, FPGAs play a vital role for early adopters of technology who want to design 100G production systems. As a result of increasing demand for more bandwidth, service providers are looking at emerging 40-GbE/100-GbE standards for their next-generation line card options. Altera Stratix V FPGAs solve the bandwidth problem by providing integrated 12.5-Gbps transceivers with hardened 100G PCS functions on the 28nm technology node.

Two qualities are important in a network: speed and reliability. Not only must the network be up all the time, it must also be fast. However, the load on networks has increased tremendously. Data is a minor component of what the network carries; voice, sound, and multimedia now form the major components. According to the Cisco Visual Networking Index (VNI) Forecast, annual global IP traffic will reach two-thirds of a zettabyte (trillion gigabytes) by 2013. This number represents more than a five fold increase over today’s IP traffic. Video will account for 90 percent of the traffic growth in 2013.

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100G system designs are gaining popularity as bandwidth requirements continue to grow exponentially. Altera’s 28nm Stratix V FPGAs offer designers an ideal FPGA solution for 40-GbE/100-GbE systems by delivering the highest density FPGAs with integrated 12.5-Gbps transceivers and hardened industry-standard IP. Stratix V transceivers support the emerging 100-GbE standards and proprietary serial protocols with line rates up to 28 Gbps. Stratix V FPGAs are specifically built to meet the requirements of next-generation 100-GbE system designs, thereby offering system designers an accelerated time-to-market advantage with reduced risk compared to ASIC or ASSP solutions. By using Stratix V FPGAs, designers can implement current 100-GbE standards and easily adapt their designs to future enhancements.

More info: Addressing 100-GbE Line-Card Design Challenges on 28nm FPGAs (pdf)