Xilinx Defense-Grade Virtex-6Q FPGA Includes Anti-Tamper Protection
The Xilinx Virtex-6Q Field Programmable Gate Array (FPGA) family is a high performance defense-grade, programmable solution for major defense applications. The combination of Virtex-6Q FPGA with the Xilinx Security Monitor (SECMON) IP core provides a secure platform for Aerospace and Defense (A&D) designs used in critical AT applications. The SECMON IP core offers a level of Anti-Tamper (AT) protection that will further strengthen the secure capabilities of the Virtex-6Q family of FPGAs.
Xilinx Defense-Grade Virtex-6Q FPGA Includes Anti-Tamper Protection »
Lattice Semiconductor Introduces Sony IMX136 Image Sensor Bridge
Lattice Semiconductor introduced the Sony IMX136 image sensor bridge. The new image sensor bridge design utilizes the low power, low cost Lattice MachXO2 PLD (programmable logic device) to interface to the Sony IMX136 image sensor. The Sony IMX136 image sensor bridge design helps engineers to quickly introduce cameras based on the Sony IMX136. The image sensor bridge design is available now for download, and the MachXO2-1200 PLD is in full production.
Lattice Semiconductor Introduces Sony IMX136 Image Sensor Bridge »
SynaptiCAD Improves VeriLogger Extreme Verilog Simulator
SynaptiCAD rolled out a new version of VeriLogger Extreme, which is a Verilog simulator. For a limited time, SynaptiCAD will give away free “no strings attached” six-month licenses for VeriLogger Extreme. Free licenses will be available for both Linux and Windows versions of the simulator. Unlike the lower cost simulators typically provided with FPGA tools, SynaptiCAD’s simulator is being distributed without any code that slows down the simulator when run on larger designs.
Altera, TSMC Use CoWoS Process to Create Heterogeneous 3D IC Test Vehicle
Altera and TSMC teamed on a heterogeneous 3D IC test vehicle. The process uses TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) integration process. Altera is the first semiconductor company to develop and complete characterization of a heterogeneous test vehicle using TSMC’s CoWoS process. This and additional test vehicles enable Altera to quickly test the capabilities and reliability of 3D ICs to ensure they meet yield and performance targets.
Altera, TSMC Use CoWoS Process to Create Heterogeneous 3D IC Test Vehicle »
Blue Pearl Software Suite Supports Synopsys Synplify Pro FPGA Synthesis
Blue Pearl Software Suite now supports Synopsys’ Synplify Pro FPGA synthesis software for VHDL and SystemVerilog designs. Blue Pearl Software collaborated with Synopsys to create an optimized flow that works with Synplify Pro FPGA synthesis software. VHDL and SystemVerilog designers are now able to automatically generate an exhaustive set of constraints that address false and multi-cycle paths and that work with Synopsys’ synthesis flow.
Blue Pearl Software Suite Supports Synopsys Synplify Pro FPGA Synthesis »
HuMANDATA Introduced the AP68-04 FPGA Module
HuMANDATA introduced their AP68-04 FPGA Module. The stamp size PLCC FPGA module features an Altera Cyclone III FPGA, two Vccio groups, an on-board 50MHz oscillator, two user LEDs, one user switch, a Power-on Reset IC, and a configuration device. The AP68-04 can be equipped on universal boards by using a 68-pin DIP IC socket. The HuMANDATA board operates with only 3.3V power supply and has an on-board 1.2V and 2.5V regulators. In addition, it is compliant with the RoHS Directive, and is designed for lead-free soldering.
Lattice iCE40 mobileFPGA Devices Support MIPI Battery Interface Standard
Lattice Semiconductor has adopted the MIPI Battery Interface (BIF) standard within the iCE40 mobileFPGA family of products. As an industry-created and adopted standard, the MIPI BIF single-wire specification accelerates the design and use of smart batteries in mobile devices. Lattice Semiconductor is engaged with key customers on the MIPI BIF standard. They plan to make support broadly available through its IP suite during the first half of this year. The MIPI BIF solutions will be free of charge to customers with high-volume mobile applications.
Lattice iCE40 mobileFPGA Devices Support MIPI Battery Interface Standard »
Aldec Releases Riviera-PRO 2012.02 for FPGA and ASIC Verification
Aldec released version 2012.02 of their Riviera-PRO. The latest version of the mixed-language verification tool supports a number of advanced verification methodologies that will benefit the designers of complex FPGAs and those migrating to ASIC. Riviera-PRO v2012.02 supports the verification environments constructed with the Universal Verification Methodology (UVM) class library and new SystemVerilog IEEE 1800-2009 and VHDL IEEE 1076-2008 constructs. This makes Riviera-PRO an ideal platform for working with the Open Source VHDL Verification Methodology (OS-VVM).
Aldec Releases Riviera-PRO 2012.02 for FPGA and ASIC Verification »
Lattice HDR-60 Video Camera Development Kit Includes New Helion GUI
Lattice Semiconductor had upgraded their HDR-60 Video Camera Development Kit. The Lattice HDR-60 is now enhanced with a Helion Graphical User Interface (GUI). The new GUI makes the engineer’s job even easier. It offers ease-of-use while improving design accuracy, further enhancing the user experience. The enhanced HDR-60 GUI will be available for download next week at no additional charge to current and new customers of the Lattice HDR-60 Video Camera Development Kit.
Lattice HDR-60 Video Camera Development Kit Includes New Helion GUI »
MathWorks Launches HDL Coder and HDL Verifier HDL Code Generation Tools
MathWorks introduced HDL Coder and HDL Verifier. HDL Coder automatically generates HDL code from MATLAB and helps engineers implement FPGA and ASIC designs from the MATLAB language. HDL Verifier features FPGA hardware-in-the-loop capabilities for testing FPGA and ASIC designs. HDL Coder and HDL Verifier are available now. Pricing for HDL Verifier starts at $3,250 and pricing for HDL Coder starts at $10,000. With HDL Verifier and HDL Coder, MathWorks now provides HDL code generation and verification across their MATLAB and Simulink tools.
MathWorks Launches HDL Coder and HDL Verifier HDL Code Generation Tools »
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