Reflex CES introduced their FPGA Aurora-like 64B/66B IP core. The new IP assures interoperability between all leading FPGAs, whatever the performance of their backplanes and systems, from 1 to 14Gbps, and whatever the generic or configurable features incorporated. The Reflex CES Aurora-like 64B/66B IP Cores are available with encrypted or VHDL source code license agreements, encrypted test-benches, reference designs and a user guide.
CAST announced the H.264 Video Over IP – HD Encoder Subsystem. The reusable subsystem makes it easier to build video streaming into mobile and other products. Reference designs for the streaming subsystem are available now for the Altera Stratix IV and Arria V families, and the Xilinx Kintex-7 line. These include the CAST and other essential IP cores implemented in an FPGA, plus the necessary interfaces, memory, drivers, and software.
Analog Devices recently launched the JESD204B Xilinx Transceiver Debug Tool. The FPGA-based reference design with software and HDL code reduces the design risk of high-speed systems incorporating JESD204B-compatible converters. It supports the 312.5-Mbps to 12.5-Gbps JESD204B data converter-to-FPGA serial data interface and Xilinx Inc., 7 series FPGAs and Zynq-7000 All Programmable SoCs.
Altera introduced five new low-cost development kits based on its Cyclone V FPGAs. The Altera kits make it easy for designers to cost-effectively get started on FPGA development with an entry point of just $49. Altera’s portfolio of low-cost CPLDs, FPGAs and SoCs are available now in production. All low-cost development kits supporting the portfolio are available today.
Lattice Semiconductor recently introduced their ultra-low density MachXO3 Field Programmable Gate Array family. The new FPGA devices are the world’s smallest, lowest-cost-per I/O programmable platform aimed at expanding system capabilities and bridging emerging connectivity interfaces using both parallel and serial I/O. First production of the MachXO3 device shipments are scheduled for the end of 2013. Prices start below $1 in high volume.
Breker Verification Systems introduced their TrekSoC-Si tool for automatically generates multi-threaded, multi-processor, self-verifying C test cases that run on the SoC’s embedded processors on in-circuit emulation (ICE) platforms, field programmable gate array (FPGA) prototypes and production silicon. The tool eliminates the need to hand-write tests for embedded processors in simulation and acceleration. TrekSoC-Si is shipping now.
Xilinx introduced their Virtex-7 FPGA VC709 Connectivity Kit. The tool is a 40 Gbps platform that enables designers to accelerate design productivity for high-bandwidth and high-performance applications, such as network interface cards for security, network monitoring, and high frequency trading appliances. The Virtex-7 FPGA VC709 Connectivity Kit is available now for shipping. It is priced at $4,995.
Microsemi introduced the IGLOO2 FPGA Evaluation Kit. The low-cost kit is a PCI Express (PCIe) compliant form factor evaluation platform. The IGLOO2 FPGA Evaluation Kit is available now for an introductory price of $99 (for the first 1,000 orders). The kit includes Microsemi’s Libero SoC Gold Software License for designing with Microsemi FPGAs and SoC FPGAs.
ASSET InterTech published a new ebook that explains how cost-effective verification of system clocks during prototype circuit board bring-up and manufacturing can be accomplished with several different methods based on JTAG and boundary-scan testing or IP in an FPGA. The title of the ebook is Testing System Clocks with Boundary Scan (JTAG) and an FPGA.
Xilinx and Analog Devices have achieved JESD204B interoperability between Xilinx JESD204 LogiCORE IP in the Kintex-7 FPGA and the ADI AD9250 analog-to-digital high-speed data converter. The results confirm that off-the-shelf ADI JESD204B data converters and Xilinx FPGAs work together seamlessly. The interoperability means manufacturers can take advantage of JESD204B to accelerate time-to-market for their new products by shortening development time, reducing system test effort, and minimizing development issues.