Actel Libero IDE Supports Windows 7
Actel recently releases Service Pack 2 for the Libero Integrated Design Environment (IDE) v9.0. The new release features support for Windows 7. The latest release of the software toolset also include features for SmartFusion intelligent mixed signal FPGAs and RTAX-DSP FPGAs. The newest release of Libero IDE offers FPGA designers ease-of-use, design performance improvement, and silicon feature exploitation capabilities, enabling them to meet design objectives faster.
Synopsys Synplify and Synplify Pro Synthesis Tools for Lattice
Synopsys and Lattice Semiconductor have agreed to a multi-year extension to their agreement. Under the terms of the OEM agreement, Lattice Semiconductor will provide specific versions of Synopsys’ Synplify Pro and Synplify software as part of its programmable logic design environments (including the Lattice Diamond FPGA design platform). The logic synthesis partnership will benefit designers targeting Lattice CPLD and FPGA products.
Synopsys Synplify and Synplify Pro Synthesis Tools for Lattice »
SynaptiCAD Upgrades WaveFormer Lite
SynaptiCAD rolled out an upgraded version of WaveFormer Lite. WaveFormer Lite is an entry level tool that can generate VHDL and Verilog stimulus-based test benches for the Actel Libero design software and other FPGA/ASIC vendor flows without requiring any special runtime engines. WaveFormer Lite fits seamlessly into Actel’s design environment, automatically extracting signal information from your HDL design files, and producing HDL test bench code that can be used with any standard VHDL or Verilog simulator.
Xilinx at NIWeek 2010
During National Instruments NIWeek 2010, Xilinx will offer demonstrations and technical sessions based on the LabVIEW FPGA Module. The sessions will focus on aerospace, industrial, medical and wireless applications. Xilinx will also show how their rad-hard Virtex-5QV FPGA is ideal for space applications. NIWeek 2010 will take place August 3-5 at the Austin, Texas Convention Center. The event focuses on graphical system design.
ZTEX USB FPGA Module 1.11
The ZTEX USB FPGA Module 1.11 is a Xilinx Spartan 6 FPGA board with USB 2.0 microcontroller and 64 MByte DDR SDRAM. The USB FPGA Module is available now for 109 EUR / 139.52 USD. An open source firmware development kit with platform independent host software API is available for the USB-FPGA-Module. The SDK egnineers to define all USB device descriptors with only a few macro commands. The kit gives developers a quick start into firmware programming.
Analog Devices Mixed Signal Digital Pre-Distortion Development Board
Analog Devices (ADI) and Xilinx announced the MS-DPD (mixed-signal, digital pre-distortion) development platform. MS-DPD helps multi-carrier cellular base station manufacturers reduce engineering resources and improve time to market. Xilinx’s Virtex-6 FPGA ML605 (field-programmable gate array) Evaluation Kit connects to the MS-DPD board through an industry-standard VITA-57 FMC connector. Using this system, the FPGA can be used to implement required radio algorithms leveraging the ADI signal chain available on the MS-DPD. The ADI MS-DPD development boards are available now for $3,995 each.
Analog Devices Mixed Signal Digital Pre-Distortion Development Board »
Actel FlashPro4 Programmer for IGLOO, ProASIC3, SmartFusion, Fusion FPGA
Actel introduced FlashPro4 hardware programmer for IGLOO series and ProASIC3 series (including RT ProASIC3), SmartFusion and Fusion flash FPGA families. FlashPro4 also supports FPGA embedded software program and debug managed by Actel’s SoftConsole Integrated Design Environment (IDE) for embedded processors. Actel’s FlashPro4 programmer is now available for US $49. The kit includes a USB cable, a ribbon cable with 10-pin JTAG connector, and a quickstart card. The FlashPro software is available for free, either standalone or as part of all Actel Libero Integrated Design Environment (IDE) versions.
Actel FlashPro4 Programmer for IGLOO, ProASIC3, SmartFusion, Fusion FPGA »
Xilinx ISE Design Suite 12.2 and Partial Reconfiguration FPGA Flow
Xilinx introduced ISE Design Suite 12.2 and the fourth generation partial reconfiguration design flow. ISE Design Suite 12.2 features lower power consumption, reduced overall system costs, and a low-cost simulation solution for the embedded design flow. ISE Design Suite 12.2 is now available for all ISE Editions with list prices starting at $2,995 for the Logic Edition. Fourth generation Partial Reconfiguration can be purchased as an option and is bundled with two days of onsite training.
Xilinx ISE Design Suite 12.2 and Partial Reconfiguration FPGA Flow »
Altera Stratix V FPGA Devices Support RLDRAM 3 Memory
Altera have optimized their Stratix V FPGA devices to support Micron Technology’s reduced-latency DRAM (RLDRAM 3 memory). The changes made to the Stratix V memory architecture make the memory interface ideal for high performance networking applications. RLDRAM 3 memory is designed to meet the requirements of high-bandwidth networking applications and enable a faster, more efficient transfer of data over the network.
Pico Computing Cracks NTLM Authentication Protocol with FPGA Devices
Pico Computing has successfully accelerated cracking of the NTLM (NT LAN Manager) authentication protocol, resulting in performance of over 144 billion keys per second. Pico Computing used a cluster of 36 Xilinx FPGA devices installed in a single 4U system consuming under 1500 watts. This compares with typical performance of less than 20 million keys per second using a modern dual-core CPU, or 250 million keys per second when using a GPU-accelerated system.
Pico Computing Cracks NTLM Authentication Protocol with FPGA Devices »
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