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Actel SmartFusion Evaluation and Development Kits

Posted by Ken Cheung in Tool on Tuesday, March 2, 2010

Actel introduced development tools for the SmartFusion intelligent mixed signal FPGAs. The development environment includes the Libero Integrated Design Environment (IDE) v9.0 with Synplify Pro and Identify from Synopsys, ModelSim from Mentor Graphics, and SoftConsole v3.1, Keil and IAR Systems software IDEs, plus access to leading RTOS and middleware from Micrium. The SmartFusion Evaluation Kit is available now for $99. The SmartFusion Development Kit is available now for $999.

Actel SmartFusion Evaluation and Development Kits »

inrevium TB-6V-LX240T, LX365T, LX550T, SX475T-PCIEXP FPGA Platforms

Posted by Ken Cheung in Tool on Thursday, February 25, 2010

Tokyo Electron Device (TED) introduced the inrevium TB-6V-LX240T, LX365T, LX550T, and SX475T-PCIEXP series FPGA evaluation platforms. The FPGA evaluation platform features either Virtex-6 LXT or Virtex-6 SXT FPGA devices, 8-lane PCI Express Gen 2 interface, and 2-channel 1066 Mbps DDR3 SDRAM SO-DIMM high-speed memory interfaces. The inrevium TB-6V-LX240T, LX365T, LX550T, and SX475T-PCIEXP series will be available in mid-March 2010. The inrevium TB-6V- LX240T, LX365T, LX550T, and SX475T-PCIEXP are ideal for the development of high-performance graphics engines for next-generation televisions and multi-function printers, or for the high-speed arithmetic processing found in high-performance computing applications.

inrevium TB-6V-LX240T, LX365T, LX550T, SX475T-PCIEXP FPGA Platforms »

FPGA Virtual Summit

Posted by Ken Cheung in Event on Wednesday, February 24, 2010

The FPGA Virtual Summit will take place 10:00 AM EDT on March 18, 2010. The FPGA Virtual Summit features five webinars. The webcast sessions cover key topics for FPGA design engineers, system architects, and engineering decision makers. The online event includes an executive round table that will discuss the future of FPGAs.

FPGA Virtual Summit »

Altera Ships 40nm Arria II GX EP2AGX45 and EP2AGX65 FPGA Devices

Posted by Ken Cheung in FPGA on Wednesday, February 24, 2010

The first members of Altera’s 40nm Arria II GX FPGA family is now shipping in volume production. The Arria II GX FPGAs now shipping in production include the EP2AGX45 and the EP2AGX65, featuring 45K logic elements (LEs) and 65K LEs, respectively. The Arria II GX device family is a low-power, low-cost and high-performance FPGA solution specifically targeting 3-Gbps transceiver applications.

Altera Ships 40nm Arria II GX EP2AGX45 and EP2AGX65 FPGA Devices »

Xilinx 28nm High-Performance, Low-Power Process for FPGA Devices

Posted by Ken Cheung in FPGA on Tuesday, February 23, 2010

The exorbitant cost of designing and manufacturing ASICs, rapidly evolving standards, the need to reduce bill of materials, and the need for both hardware and software programmability, all in the face of rough economic times and reduced staffing – are converging to create an environment where electronics product designers are increasingly looking to FPGAs as alternatives to ASICs and ASSPs. Xilinx calls the convergence of these trends the Programmable Imperative.

Xilinx 28nm High-Performance, Low-Power Process for FPGA Devices »

GateRocket RocketVision 5.0 FPGA Debug Solution

Posted by Ken Cheung in Tool on Tuesday, February 23, 2010

GateRocket launched version 5.0 of the RocketVision debugging software. RocketVision 5.0 enables engineers to select individual design blocks to run in their simulator or GateRocket’s RocketDrive hardware verification system. RocketVision 5.0 helps designers find and fix bugs faster, and avoid unnecessary re-runs of time-consuming synthesis-to-place-and-route iterations, reducing overall design bring-up time by 50% or more compared to traditional approaches. RocketVision 5.0 is a RocketDrive option and is available immediately with a starting price of $9,500.

GateRocket RocketVision 5.0 FPGA Debug Solution »

Xilinx Selects Samsung Foundry 28nm HKMG Process Technology for FPGA

Posted by Ken Cheung in Other on Tuesday, February 23, 2010

Xilinx selected Samsung Electronics as their foundry partner for 28nm high-k metal gate (HKMG) process technology manufacturing optimized for a balance of performance and power efficiency. The 28nm HKMG process technology of Samsung Foundry enables Xilinx to implement a new generation of FPGAs that offer up to 50% lower power savings over devices built on the previous 45nm technology node.

Xilinx Selects Samsung Foundry 28nm HKMG Process Technology for FPGA »

Actel at Embedded World 2010

Posted by Ken Cheung in Event on Tuesday, February 23, 2010

Actel will demonstrate embedded technologies and mixed-signal FPGAs at the Embedded World 2010 exhibition and conference (March 2-4, 2010 in Nuremberg, Germany). At Embedded World, designers will learn how Actel’s solutions offer embedded system designers the ability to integrate multiple functions and applications into a single device, and offer maximum flexibility, faster time-to-market and reduced power consumption.

Actel at Embedded World 2010 »

CoWare SPW 2010.1 Release

Posted by Ken Cheung in Tool on Monday, February 22, 2010

CoWare announced the 2010.1 release of CoWare SPW products. The SPW 2010.1 release advances the LTE (Long Term Evolution) Wireless Reference Library and adds a complete Xilinx implementation flow that includes direct source translation technology from C Data Flow (CDF) into RTL. The CoWare SPW 2010.1 release is available immediately. With this release, CoWare has reverted back to the product’s original SPW name (previously Signal Processing Designer, SPD).

CoWare SPW 2010.1 Release »

Programming High Performance Signal Processing Systems

Posted by Ken Cheung in Event on Monday, February 22, 2010

Vinod Kathail, Chief Technology Officer at Synfora, will take part in a panel discussion at the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2010). The panel will discuss the use of high-level languages in the programming of high-performance signal processing systems for FPGAs. The event will take place Monday, February 22, 2010 at the Monterey Beach Resort in Monterey, California.

Programming High Performance Signal Processing Systems »

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