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Xilinx Targets 3D and 4K2K Displays with Reference Designs and ACDC Baseboard

Posted by Ken Cheung in FPGA-based Product,Reference Design,Tool on Thursday, January 5, 2012

Xilinx introduced reference designs and a development baseboard for speeding the development of next-generation, 3D and 4K2K display technologies. The 4K2K Mosaic and HDTV-to-4K2K up-converter targeted reference designs are based on the new 28nm Kintex-7 Field Programmable Gate Array (FPGA). The new ACDC (Acquisition, Contribution, Distribution and Consumption) 1.0 Baseboard also uses Kintex-7 FPGA devices. The targeted reference designs and ACDC 1.0 Baseboard with the Kintex-7 FPGA will be available in Q2 2012.

Xilinx Targets 3D and 4K2K Displays with Reference Designs and ACDC Baseboard »

D.SignT D.Module2.Base-FMC Board Supports Two Modular Standards

Posted by Ken Cheung in Tool on Wednesday, January 4, 2012

Thanks to the D.Module2.Base-FMC from D.SignT, developers can combine D.Module DSP and FPGA boards with Ansi Vita S7 compliant FMC modules. D.SignT’s D2-Base-FMC is a prototyping and evaluation platform for the D.Module2 family of DSP and FPGA boards. The D.Module2 standard allows stacking of modules so both an FPGA and a DSP module can be used for processing data for the same application. The board’s Ansi Vita 57 compliant FMC LPC IO site enables it to be used with industry-standard mezzanine boards (such as A/D and D/A data acquisition, video and camera interfaces, and digital radio frontends).

D.SignT D.Module2.Base-FMC Board Supports Two Modular Standards »

Cornell University Students Create Interesting FPGA Projects

Posted by Ken Cheung in Other on Thursday, December 22, 2011

Every year, the brilliant students at Cornell University work on some fabulous projects for their ECE 5760. The students were given the responsibility of choosing their project, then designing and building it. Projects were built using the Altera/Terasic DE2 Development and Education board. This year’s projects include: prime number generator and RSA encrypter/decrypter, Conway’s life synthesizer, hand video-tracking virtual piano and drums, finger video-tracking virtual string instrument, and hand video-tracking video game.

Cornell University Students Create Interesting FPGA Projects »

CAST UDPIP IP Core

Posted by Ken Cheung in IP Core on Tuesday, December 20, 2011

CAST introduced the UDPIP IP core. The CAST UDPIP is a hardware implementation of the User Datagram Protocol (UDP), which is a fast, simple, transport layer protocol that works without the handshaking and error correction of the more rigorous Transmission Control Protocol (TCP). The UDPIP IP core is available now in Verilog or as an optimized netlist for Altera and Xilinx FPGAs. Integration with MAC cores from CAST, FPGA vendors, or other sources is available. Integration with CAST compression cores (e.g., the H.264 encoder) is also available.

CAST UDPIP IP Core »

Lattice Diamond Design Software v1.4

Posted by Ken Cheung in Tool on Thursday, December 15, 2011

Lattice Semiconductor introduced version 1.4 of the Lattice Diamond design software. Lattice Diamond v1.4 features several usability enhancements that make FPGA design exploration easier and reduce time to market. Lattice Diamond v1.4 software is available now for for both Windows and Linux. Once downloaded and installed, the software can be used with either the Lattice Diamond free license or the Lattice Diamond subscription license. The Lattice Diamond free license provides no cost access to many Lattice devices such as the MachXO2 and MachXO device families, the LatticeXP2 and LatticeECP2 FPGA families, and the Platform Manager devices. The Lattice Diamond free license enables Synopsys Synplify Pro for Lattice synthesis as well as the Aldec Lattice Edition II mixed language simulator.

Lattice Diamond Design Software v1.4 »

Avnet Spartan-6 FPGA Motor Control Development Kit

Posted by Ken Cheung in Tool on Wednesday, December 14, 2011

Avnet Electronics Marketing introduced the Spartan-6 FPGA Motor Control Development Kit. The Avnet kit helps designers prototype motor control designs for applications in industrial automation, consumer electronics, medical diagnostics and robotics. The Avnet Spartan-6 FPGA Motor Control Development Kit is an ideal platform for engineers seeking to experiment with proven reference designs and develop custom control, integrating flexible peripheral functions like Ethernet, PowerLink and PCI Express (PCIe).

Avnet Spartan-6 FPGA Motor Control Development Kit »

Lattice Semiconductor Acquires SiliconBlue Technologies for $62 Million

Posted by Ken Cheung in FPGA on Tuesday, December 13, 2011

Lattice Semiconductor will acquire SiliconBlue Technologies for about $62 million in cash. According to Lattice, the acquisition of SiliconBlue is aligned with their strategic long range plan and will help accelerate their growth strategy in the mobile consumer market. Silicon Blue will further strengthen Lattice’s product roadmap by adding a scalable, low cost, low power nonvolatile memory FPGA, along with key personnel and blue chip customers.

Lattice Semiconductor Acquires SiliconBlue Technologies for $62 Million »

Lattice Semiconductor PAC-Designer Mixed Signal Design Software v6.2

Posted by Ken Cheung in Tool on Monday, December 12, 2011

Lattice Semiconductor rolled out version 6.2 of their PAC-Designer mixed signal design software. PAC-Designer 6.2 features updated support for Lattice’s Platform Manager, Power Manager II and ispClock devices, reduced LogiBuilder code size, simplified design flow and better access to external Platform Manager pin-to-pin connections. PAC-Designer v6.2 can be downloaded now for free. PAC-Designer 6.2 software does not require a separate license file.

Lattice Semiconductor PAC-Designer Mixed Signal Design Software v6.2 »

Innovative Integration Unveils PEX6-COP FPGA Co-processor Card

Posted by Ken Cheung in FPGA-based Product on Thursday, December 8, 2011

Innovative Integration introduced their PEX6-COP FPGA co-processor card. The flexible board features an integrated FPGA computing core with an industry-standard FMC IO module on a half-length PCI Express desktop or server card. The FPGA computing core supports the Xilinx Virtex 6 FPGA family in densities up to LX550 and SX475. The SX475 offers over 2000 DSP MAC elements operating at up to 500 MHz. The FPGA core has two 9MB QDRII+ SRAM banks, two 256MB LPDDR2 DRAM banks, and a 128MB DDR3 bank. Each memory is directly connected to the FPGA and is fully independent.

Innovative Integration Unveils PEX6-COP FPGA Co-processor Card »

Microsemi Offers Private Label Program for SmartFusion cSoC and FPGA

Posted by Ken Cheung in FPGA-based Product on Wednesday, December 7, 2011

Microsemi announced a private labeling program for their SmartFusion customizable system-on-chip (cSoC), and flash and antifuse-based FPGA solutions. Microsemi’s new private label program enables companies to rapidly deliver economical and differentiated system-on-chip solutions. With the company’s SmartFusion cSoC devices, engineers can reduce the size of their circuit boards and the external bill-of-material component count while at the same time increasing the mean time between failure.

Microsemi Offers Private Label Program for SmartFusion cSoC and FPGA »

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