Xilinx to Discuss Stacked Silicon Interposer Technology at DesignCon 2012
At DesignCon 2012, Xilinx will discuss the benefits and drawbacks of 3D IC standards. Xilinx will also present papers on Stacked Silicon interposer technology and the design benefits of using the Zynq-7000 Extensible Processing Platform (EPP). In addition, Xilinx will also demonstrate the latest Xilinx FPGA platforms featuring advanced Digital Signal Processing (DSP) performance, low power, FMC migration, high-speed connectivity, and Xilinx’s Agile Mixed Signal (AMS) Analog-to-Digital Converter (ADC). DesignCon 2012 will take place January 30 – February 2, 2012 in Santa Clara, California.
Xilinx to Discuss Stacked Silicon Interposer Technology at DesignCon 2012 »
Aldec ALINT 2012.01 Includes Documentation Support for Safety-Critical Designs
Aldec rolled out ALINT 2012.01. The latest version features documentation support that addresses the strict guidelines placed on various safety-critical industries such as DO-254 for avionics, IEC 61508/61513 for nuclear and ISO 26262 for automotive. The ability to generate a report with complete analysis of detected violations and justification of waivers can help engineers decrease the effort in documentation and reporting. ALINT 2012.01 with support for VHDL or Verilog DO-254 design rule plug-in is available now.
Aldec ALINT 2012.01 Includes Documentation Support for Safety-Critical Designs »
Altera to Share Solutions at DesignCon 2012
At DesignCon 2012, Altera will showcase how they are solving some of the industry’s most complex design challenges through 28nm FPGA architectural innovations and advanced technologies that enable high-speed I/O performance, floating point DSP and best-in-class signal integrity. Altera will participate on industry panels, conduct a TechForum tutorial and present nine conference papers. DesignCon will take place January 30 to February 2, 2012 at the Santa Clara Convention Center in California.
LatticeECP3 FPGA Devices in Low Power, High Speed, and Small Packages
Lattice Semiconductor Corporation is offering low power, high speed, and small form-factor versions of their LatticeECP3 FPGA devices. The new packaging helps engineers create power and space limited applications in professional cameras, surveillance cameras, medical imaging, video communication, and small-form-factor wireline and wireless appliances. Prices for the LatticeECP3-17K Mini Device in 328csBGA package start at $4.95 (in 500K unit volume). Delivery will be in the fourth quarter of 2013.
LatticeECP3 FPGA Devices in Low Power, High Speed, and Small Packages »
Xilinx Releases ISE Design Suite v13.4
Xilinx rolled out version 13.4 of their ISE Design Suite. ISE Design Suite 13.4 features public access to the MicroBlaze Micro Controller System (MCS), new RX Margin Analysis and debug capabilities for the 28nm 7 Series FPGAs and partial reconfiguration support for the Artix-7 family and Virtex-7 XT devices. ISE Design Suite v13.4 is available now for all ISE Editions. List prices start at $2,995 for the Logic Edition.
Lattice Semiconductor, Aptina Team on Dual Image Sensor Stereo Camera Reference Design
Lattice Semiconductor and Aptina will showcase a low cost, dual image sensor design at the Consumer Electronics Show (CES) in Las Vegas, January 10-13, 2012. The dual image sensor design helps ISP vendors to quickly offer multiple camera solutions for the consumer market. Lattice’s private hospitality meeting suite will be held in the Las Vegas Hilton, North Hall, 28th Floor, Suite 127.
Lattice Semiconductor, Aptina Team on Dual Image Sensor Stereo Camera Reference Design »
Xilinx Targets 3D and 4K2K Displays with Reference Designs and ACDC Baseboard
Xilinx introduced reference designs and a development baseboard for speeding the development of next-generation, 3D and 4K2K display technologies. The 4K2K Mosaic and HDTV-to-4K2K up-converter targeted reference designs are based on the new 28nm Kintex-7 Field Programmable Gate Array (FPGA). The new ACDC (Acquisition, Contribution, Distribution and Consumption) 1.0 Baseboard also uses Kintex-7 FPGA devices. The targeted reference designs and ACDC 1.0 Baseboard with the Kintex-7 FPGA will be available in Q2 2012.
Xilinx Targets 3D and 4K2K Displays with Reference Designs and ACDC Baseboard »
D.SignT D.Module2.Base-FMC Board Supports Two Modular Standards
Thanks to the D.Module2.Base-FMC from D.SignT, developers can combine D.Module DSP and FPGA boards with Ansi Vita S7 compliant FMC modules. D.SignT’s D2-Base-FMC is a prototyping and evaluation platform for the D.Module2 family of DSP and FPGA boards. The D.Module2 standard allows stacking of modules so both an FPGA and a DSP module can be used for processing data for the same application. The board’s Ansi Vita 57 compliant FMC LPC IO site enables it to be used with industry-standard mezzanine boards (such as A/D and D/A data acquisition, video and camera interfaces, and digital radio frontends).
D.SignT D.Module2.Base-FMC Board Supports Two Modular Standards »
Cornell University Students Create Interesting FPGA Projects
Every year, the brilliant students at Cornell University work on some fabulous projects for their ECE 5760. The students were given the responsibility of choosing their project, then designing and building it. Projects were built using the Altera/Terasic DE2 Development and Education board. This year’s projects include: prime number generator and RSA encrypter/decrypter, Conway’s life synthesizer, hand video-tracking virtual piano and drums, finger video-tracking virtual string instrument, and hand video-tracking video game.
Cornell University Students Create Interesting FPGA Projects »
CAST UDPIP IP Core
CAST introduced the UDPIP IP core. The CAST UDPIP is a hardware implementation of the User Datagram Protocol (UDP), which is a fast, simple, transport layer protocol that works without the handshaking and error correction of the more rigorous Transmission Control Protocol (TCP). The UDPIP IP core is available now in Verilog or as an optimized netlist for Altera and Xilinx FPGAs. Integration with MAC cores from CAST, FPGA vendors, or other sources is available. Integration with CAST compression cores (e.g., the H.264 encoder) is also available.
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