Xilinx Spartan-6 LX16 Evaluation Kit
At the heart of the Xilinx Spartan-6 LX16 FPGA Evaluation Board is a Cypress PSoC 3 programmable system-on-chip. The PSoC 3 device integrates precision analog sensing, system management and user interface functions. The PSoC 3 device performs power management, CapSense touch-sensing, USB/UART/SPI connectivity and configuration of the Field Programmable Gate Array (FPGA) directly on the board. Flexible PSoC 3 I/Os also enable the board to interface to the analog world through an expansion connector that accepts an included Avnet LCD board, user prototype boards and various Cypress expansion boards.
Impulse C to FPGA Toolset for Stone Ridge RDX-11 FPGA Board and Kit
Stone Ridge Technology and Impulse Accelerated Technologies teamed together to integrate Impulse C to FPGA toolset with Stone Ridge’s RDX-11 FPGA board and development kit. The integration enables software developers to write HLL (high level language) algorithms that rapidly compile to optimized RTL (run time language). Developers can purchase Impulse C or Stone Ridge boards from the respective manufacturers.
Impulse C to FPGA Toolset for Stone Ridge RDX-11 FPGA Board and Kit »
Digital Signal Processing, FPGA, and Embedded Processors Training
qaqadu announced three technical short courses starting in October 2010. The training courses are: FPGAs for Embedded Processors (October 12-14, 2010); DSP for FPGAs (November 16-19, 2010); and DSP Theory, Algorithms and Architectures (December 7-10, 2010). After each presentation, a hands-on session will follow in which engineers will be able to simulate and implement the structures and architectures introduced. The events will take place in Munich, Germany. The classes will be in English. All attendees will receive electronic and printed versions of the teaching materials. A DVD containing all the simulation models used during the course will also be distributed.
Digital Signal Processing, FPGA, and Embedded Processors Training »
FPGA-Based System Design with High-Speed Data Converters Workshops
Avnet Electronics Marketing Americas (EMA), MathWorks, and Texas Instruments (TI) are offering a series of workshops on digital signal processing (DSP) system design using Xilinx FPGAs with high-speed data converters. The two-day workshops will take place throughout North America. Engineers attending the workshop will receive a coupon or discount for their choice of either: $400 off an AES-V6DSP-LX240T-G Xilinx Virtex-6 FPGA DSP Development Kit or an AES-S6DSP-LX150T-G Xilinx Spartan-6 FPGA DSP Development Kit. Attendees will also receive $650 off a TI TSW4200 Dual ADC and Dual DAC Development Platform for Xilinx Virtex-6 and Spartan-6 FPGAs or any other combination of compatible TI high-speed converter EVMs.
FPGA-Based System Design with High-Speed Data Converters Workshops »
SiliconBlue iCE65L01F-TCB81 and iCE65P04F-TCB121 FPGA Devices
SiliconBlue Technologies is offering their iCE65 mobileFPGA in two new device packages (iCE65L01F-TCB81 and iCE65P04F-TCB121). The new FPGA devices and SiliconBlue’s wafer-level chip scale packages are ideal for implementing a number of features including gyros, accelerometers, and dual displays. The iCE65L01F-TCB81 and the iCE65P04F-TCB121 FPGA devices are available now in volume production.
SiliconBlue iCE65L01F-TCB81 and iCE65P04F-TCB121 FPGA Devices »
RoweBots Unison Ultra Tiny Linux RTOS for Actel SmartFusion FPGA
The RoweBots Unison ultra tiny Linux compatible OS is now available for Actel SmartFusion devices. Thanks to the partnership, developers now have the option for Linux-based embedded systems when using SmartFusion intelligent mixed signal FPGAs. Unison consists of a set of modular software components that are either free or commercially licensed. All Unison versions are strictly tested with standardized POSIX test suites. Unison includes over 30 demonstration programs that work out of the box in ten minutes with SoftConsole.
RoweBots Unison Ultra Tiny Linux RTOS for Actel SmartFusion FPGA »
Innovative Integration X3-SD16 PCI Express XMC Module
Innovative Integration announced the X3-SD16 PCI Express XMC module. Data acquisition control, signal processing, buffering, and system functions are implemented in a Xilinx Spartan 3A DSP 1.8M FPGA device. Two 512Kx32 memories are used for data buffering and FPGA computing memory. The logic can be fully customized using VHDL and MATLAB via the FrameWork Logic toolset. The MATLAB BSP supports real-time hardware-in-the-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator.
Mercury Protocol Offload Engine Technology for Intel Subsystems
Mercury Computer Systems launched their Protocol Offload Engine Technology (POET) protocol-agnostic, multi-standard switch fabric technology. POET is a downloadable FPGA firmware collection of open standards technologies providing interconnectivity between boards, systems, and sensors for Mercury’s Intel-based subsystems. The technology enables scalable, high speed, and deterministic communications and I/O. POET interconnect efficiently extends the capabilities of the Intel-based subsystem. Mercury’s Protocol Offload Engine Technology is the first multi-fabric connectivity solution for Intel processors.
Mercury Protocol Offload Engine Technology for Intel Subsystems »
Lattice ispLEVER Classic 1.4 Design Tool Suite
Lattice Semiconductor launched ispLEVER Classic design tool suite, version 1.4. The upgraded ispLEVER Classic features Synopsys Synplify Pro with the HDL Analyst feature set, and an improved ispMACH 4000ZE CPLD fitter with improved power optimization. Classic 1.4 software is compatible with Windows XP/Vista/7 and operates as a 32-bit application. The ispLEVER Classic 1.4 tool suite is available now for free. Designers can also download the optional Synopsys Synplify Pro logic synthesis and Aldec Active-HDL simulator modules.
InPA Systems Develops Active Debug Technology for Rapid Prototyping
InPA Systems, Inc. is officially being launched today. The company was formed to develop and market FPGA-based rapid prototyping technology to engineers. The company integrates RTL simulation, hardware and software debug environments, provides an Active Debug methodology and enables full visibility into the multi-FPGA prototype to compress the time it takes to debug SoC designs. InPA Systems’ patent pending Active Debug feature full visibility technology to better detect hardware faults and reduce the FPGA P&R iterations associated with the debug cycle for next-generation complex SoCs.
InPA Systems Develops Active Debug Technology for Rapid Prototyping »
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